Design-Reuse

Synopsys' DesignWare DDR PHY Compiler Eases Integration of Memory Interface IP

MOUNTAIN VIEW, Calif., Jan. 26, 2011-- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the immediate ...
Design-Reuse

Core-assisted approach accelerates debug of FPGA DDR II interfaces

With IO rates of several hundred megahertz, FPGAs have become an excellent medium for implementation of high-speed memory controllers. Fast memory storage and retrieval often involve implementing DDR ...
EDN

ESC – New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces

Mountain View, Calif. – Synopsys, Inc. today announced the availability of the high-performance DesignWare Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and ...